1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of forming a storage capacitor in a stacked memory cell.
2. Description of the Prior Art
In recent years, the development of semiconductor devices in which numerous elements are integrated at a high density on a semiconductor chip has been actively under way. For the memory cell of the dynamic random access memory (DRAM), there have been proposed various structures suitable for miniaturization of the device.
Presently, the preferred memory cell from the standpoint of minimum area is the one transistor and one capacitor cell. In such a memory cell, signal charge is stored in the storage node of the capacitor (storage capacitor) connected to the transistor (switching transistor).
The storage node of the memory cell is required to have a surface area larger than a prescribed value. Therefore, further progress in the miniaturization of the memory cell makes it imperative for a storage node having a relatively large surface area to be formed within a small, restricted region on a semiconductor substrate.
The stacked memory cell in which the storage node is formed above a silicon substrate is suitable for higher integration of elements and has the advantage of being less likely to cause soft errors. Furthermore, the stacked memory cell has an advantage compared to the trench type memory cell having a trench capacitor in that the former is relatively easy to fabricate and suitable for mass production.
For the stacked memory cells, there have been proposed, for example, a memory cell having a box-like structure (S. Inoue, A. Nitayama, K. Hieda and F. Horiguchi: "A New Stacked Capacitor Cell with Thin Box Structured Storage Node", Ext. A bs. 21th SSDM, p. 141 (1989)) and a memory cell having a fin structure (T. Ema, S. Kawanago, T. Nishii, S. Yoshida, H. Nishibe, T. Yabu, Y. Komeda, T. Nakano and M. Taguchi: "3-DIMENSIONAL SPARKED CAPACITOR CELL FOR 16M and 64M DRAMS", IEDM Tech. Dig., p. 592 (1988)). Both of these memory cells have a structure in which the surface area of the storage node is larger than the area on the substrate occupied by the memory cell.
Referring to FIGS. 10A to 10G, we will now describe a prior art method of fabricating a semiconductor device having the above-mentioned box structured memory cell. FIG. 10A shows in cross section a fragmentary portion of a p-type silicon substrate 1 on which switching transistors 50 and an insulating film 40 covering the switching transistors 50 are formed.
The switching transistor 50 is an n-type MOSFET having n-type impurity diffusion layers 19 in the silicon substrate 1 and a word line 2. The word line 2 functions as the gate electrode of the switching transistor 50. The insulating film 40 has a multilayer structure in which a first silicon oxide layer 3, a silicon nitride layer 4, and a second silicon oxide layer 5 are laminated one on top of the other in this order starting from the side of the substrate 1. All of these layers are deposited by a CVD technique.
As shown in FIG. 10B, a contact hole 18 is formed in the insulating film 40 by photolithography and etching, after which a first silicon layer 6, which serves as a conductive film, is formed on top of the second silicon oxide layer 5.
A third silicon oxide layer 31, a second silicon layer 10, and a fourth silicon oxide layer 32 are deposited in this order on top of the first silicon layer 6 starting from the side of the substrate 1, to form a multi-layer film 80.
An etching mask (not shown) having a prescribed pattern is formed by photolithography on the fourth silicon oxide layer 32. Thereafter, as shown in FIG. 10C, anisotropic dry etching is repeated to pattern the multi-layer film 80 in the form corresponding to the pattern of the etching mask. Since the silicon oxide layers 31 and 32 and the silicon layers 6 and 10 are formed from different materials, it is difficult to etch the multi-layer film 80 in a single etching process under the same etching condition. Therefore, each layer constituting the multi-layer film 80 is etched under different etching conditions.
Next, a third silicon layer 33 is deposited by a CVD technique over the first silicon layer 6 in such a manner as to completely cover the multi-layer film 80.
Thereafter, the third silicon layer 33 is etched back by anisotropic etching. The etching back is continued till the surfaces of the fourth silicon oxide layer 32 and the second silicon oxide layer 5 are exposed. As a result of this etching back, the second silicon layer 10 is left only on the sides of the multi-layer film 80, thus forming the structure shown in FIG. 10D.
Next, as shown in FIG. 10E, a contact hole 18 is formed in the fourth silicon oxide layer 32 and the second silicon layer 10, reaching down to the third silicon oxide layer 31. Then, the second, third, and fourth silicon oxide layers 5, 31, and 32 are removed by etching, to form a storage node 11 as shown in FIG. 10F. A dielectric film 12 and a cell plate 13 are successively formed in such a manner as to cover the storage node 11, to form a storage capacitor as shown in FIG. 10G.
Referring to FIGS. 11A to 11G, we will now describe a prior art method of fabricating a memory cell having the previously mentioned fin structure. FIG. 11A shows in cross section a fragmentary portion of a p-type substrate 1 on which switching transistors 50 are formed. The switching transistor 50 is an n-type MOSFET having n-type impurity diffusion layers 19 and a word line 2 that also serves as the gate electrode of the switching transistor 50.
A Si.sub.3 N.sub.4 layer 15 is deposited by a CVD technique on the substrate 1 in such a manner as to cover the switching transistor 50, after which a first silicon oxide layer 60, a first silicon layer 61, and a second silicon oxide layer 62 are deposited in this order on top of the Si.sub.3 N.sub.4 layer 15 starting from the side of the substrate 1.
A contact hole 18 is formed in a multi-layer film comprising the above-mentioned layers, as shown in FIG. 11C. Thereafter, a second silicon oxide layer 63 is deposited on top of the second silicon oxide layer 62 in such a manner as to contact the n-type impurity diffusion layer 19 of the switching transistor 50 through the contact hole 18, as shown in FIG. 11D.
Next, after patterning the second silicon layer 63, the second silicon oxide layer 62 is etched away. Also, after patterning the first silicon layer 61 (FIG. 11E), the first silicon oxide layer 60 is etched away (FIG. 11F), thus forming a storage node 11 having a fin structure. Then, a dielectric film 12 and a cell plate 13 are formed in this order on top of the storage node 11, to from a storage capacitor as shown in FIG. 11G.